1. Field of the Invention
The present invention generally relates to connection modules such as chip carriers and circuit boards on which electronic chips are mounted and, more specifically, to the connections between the chips and connection modules.
2. General Description of Background
In VLSI (Very Large Scale Integration) design there is a trend to improve utilization of available circuits in order to achieve both improved performance and higher densities. To facilitate such reuse, circuits have been divided up into large functional elements known as macros, cells or blocks. Such elements are positioned on the chip much like chips are positioned on circuit boards. For example, in ASIC (Application Specific Integrated Circuits) the use of existing elements is optimized to improve density and obtain better performance.
During design refinement, as such elements are replaced and repositioned to improve performance/density, there is a need for revising the arrangement of power/signal connections of the chip, known as the footprint of the chip. Previously, however, the power/signal footprint could not be changed without reworking existing connection modules or, more likely, scrapping any existing connection modules such as circuit boards or chip carriers and redesigning, tooling and manufacturing new connection modules. Therefore, cell utilization has been less than optimum or costs have been higher due to replacement of such connection modules.
Even for chips which are not designed using macro methods, as the design is refined, unexpected contentions for input/output (I/O) of power or signals develop in the same areas of the chip so that the power/signal footprint needs to be revised to provide optimum chip design.
Previously, circuit boards have been customized for specific applications so that boards designed for one chip set could not be used for another chip set. This was true even if a similar function was to be performed. This has lead to extensive costs in redesign of circuit boards and retooling of manufacture for each new application and also in the longer lead times which redesign and retooling require.
Due to design considerations, different chips are often developed which are functionally similar. Later, in order to reduce manufacturing and inventory costs, as electronic densities on chips improve, the different chips are replaced by a single manufacture capable of being programmed for replacing either of the prior chips. For example, cutting a single trace or applying a high voltage to some contact on the chip will provide for modifying the chip to perform different functions. However, where different chips have different power/signal footprints, producing a single replacement has proved more difficult.